Logic device/transceiver/encoder

The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop can be clocked individually by holding the common clock (CC) low and using the clock enable (CEbar) input. Common timing is achieved by holding the CEbar input low and using CC to time all four flip-flops. In this case, the CEbar input performs the function of controlling a common clock for each flip-flop. A separate asynchronous reset (R) is provided. Asynchronous setup controls are grouped together in pairs, with the pairing chosen to reflect the symmetry of the physical chip. When both CC and CEbar are low, data goes to the master, and when either CC or CEbar (or both) is high, data is transferred to the slave. The 100 Series includes temperature compensation.

Low Power Single Positive Edge Triggered D-Type Flip-Flop 5-DSBGA -40 to 85

Quad D-Type Flip-Flops with Clear 16-SO -40 to 85

High Speed ​​CMOS Logic Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125

The NC7SZU04 is an unbuffered inverter from Fairchild's ultra-high-speed TinyLogic series. The dedicated unbuffered circuit design is primarily for crystal oscillator or analog applications. Fabricated using advanced CMOS technology, the device achieves ultra-high speed and high output drive while operating over a wide V

Automotive 6-Channel, 2V to 6V Inverter 14-TSSOP -40 to 85

2-Channel, 0.8V to 3.6V Low Power Inverter with Schmitt Trigger Input 6-SON -40 to 85

6-Channel, 2V to 6V Inverter with Schmitt Trigger Inputs 14-TSSOP -40 to 85