Logic device/transceiver/encoder

4-Channel, 2-Input, 2V to 6V OR Gate 14-PDIP -40 to 85

4-Channel, 2-Input, 2V to 6V XNOR (Exclusive NOR) Gate with Open-Drain Outputs 14-SO -40 to 85

2-Channel, 4-Input, 4.5V to 5.5V Bipolar NAND Gate 14-SOIC 0 to 70

Single 2-input, 1.65V to 5.5V NAND gate with open-drain output 5-SOT-23 -40 to 125

Automotive 4-Channel, 2-Input, 2V to 3.6V XOR Gate 14-TSSOP -40 to 125

The MM74HC573 high-speed octal D-type latch utilizes an advanced silicon-gate P-channel CMOS process. The device has the high noise immunity and low power consumption of a standard CMOS integrated circuit, plus the ability to drive 15 LS-TTL loads. Due to their large output drive capability and 3-state nature, these devices are suitable for interfacing bus lines in bus organizing systems. When the latch enable (LE) input is high, the Q output will follow the D input. When Latch Enable goes low, the data at the D input remains at the output until Latch Enable goes high again. Applying a high logic level to the output control (OC) input puts all outputs into a high-impedance state, regardless of the signals present at the other inputs and the state of the storage elements. The 74HC logic family is compatible with the standard 74LS logic family in speed, functionality, and pinout. All inputs are protected against damage due to electrostatic charge by internal diodes clamped to VCC and ground.