Logic device/transceiver/encoder

The MC14517B dual 64-bit static shift register consists of two identical independent 64-bit registers. Each register has individual clock and write enable inputs at 16, 32, 48, and 64. Data at the data input is clocked in regardless of the state of the write enable input. When the write enable input is high, the output is disabled (open circuit). During this time, the data displayed on the data input and 16-bit, 32-bit, 48-bit contacts can be input into the device by applying clock pulses. This feature enables registers to be loaded with 64 bits in 16 clock periods and also allows the use of bus logic. This device is used in time delay circuits, temporary memory storage circuits, and other serial shift register applications.

8-Bit Shift Register with Output Register 16-PDIP -40 to 125

8-Bit Parallel Output Serial Shift Register 14-SOIC 0 to 70