Memory chip

The CAT34C02 is an EEPROM serial 2-Kb SPD for DDR2 DIMMs, internally organized as 16 pages of 16 bytes each for a total of 256x8 bits. It has a 16-byte page write cache and supports Standard (100 kHz) and Fast (400 kHz) I2C protocols. Write operations can be inhibited by taking the WP pin high (to protect the entire memory) or by setting the internal write-protect flag (to protect the lower half of the memory) by software command. In addition to permanent software write protection, the CAT34C02 features JEDEC-compliant reversible software write protection for DDR2 sequential memory pointer detect (SPD) applications operating over a 1.7 V to 3.6 V supply voltage range. The CAT34C02 is fully backward compatible with previous DDR1 SPD applications operating on a supply voltage range of 1.7 V to 5.5 V.